This invention relates to Josephson junction circuits.
The current-voltage characteristic of a Josephson tunnel junction device is known to have an unstable region at low voltages. If one attempts to voltage bias the device in the unstable region, its operating point jumps back and forth between the supercurrent state (V=0) and the finite voltage state (V.noteq.0, typically V=2.DELTA., the gap voltage of the superconductor). This process is known as relaxation oscillations. One circuit which induces these oscillations includes a resistor R in parallel with the junction and a bias current source I.sub.b applied to the parallel combination, with the shunt resistance being sufficiently small that the load line falls within the unstable region and with I.sub.b greater than the critical current I.sub.J of the junction. When the junction switches from V=0 to V.noteq.0, the bias current diverts to the resistor, lowering the current in the junction and reducing the junction voltage to the unstable region. Here, the junction voltage returns to V=0, and the bias current flows back into the junction until it reaches I.sub.J causing the junction to switch from V=0 to V.noteq.0 again. The oscillation frequency is determined primarily by the resistance R, the inductance L of the shunting path and the ratio I.sub.b /I.sub.J. Typical frequencies range from 1 to 50 GHz. Further information on these relaxation oscillations is given by F. L. Vernon et al, Journal of Applied Physics, Vol. 39, No. 6, p. 2661 (1968).
While a Josephson junction undergoing relaxation oscillations functions as an oscillator, it can also be viewed as a self-resetting switch, a property in contrast with the latching characteristic of most Josephson junction circuits. A latching junction switches from V=0 to V.noteq.0 when I.sub.J is exceeded and remains in that state until its current is reduced below the "drop-back" or "switch-back" current I.sub.o. See U.S. Pat. No. 3,564,351 granted to D. E. McCumber on Feb. 16, 1971. This resetting mode is time consuming and, therefore, decreases the speed of the circuits severely.
Recognizing the disadvantages of latching circuits, several workers in the art have proposed nonlatching or self-resetting schemes capable of being DC powered. P. L. Gueret, in U.S. Pat. No. 4,012,642 issued on Mar. 15, 1977, chooses circuit parameters so that upon removal of an input signal the AC voltage generated across the junction in its V.noteq.0 state becomes larger than the time-averaged DC voltage across the junction. This condition insures automatic resetting of the junction to its V=0 state after removal of the input signals (column 1, lines 49-60). This technique is criticized, however, by W. Baechtold et al in U.S. Pat. No. 3,953,749 issued on Apr. 27, 1976 at column 3, lines 43-50. They state that Gueret's circuit "requires an extremely high current density within the Josephson junction and tight tolerances which are difficult to meet in practice." As an alternative Baechtold et al disclose a self-resetting circuit including a pair of series connected Josephson junctions each being shunted by a load impedance and being connected to a low impedance voltage source. That source delivers a constant voltage corresponding to the gap voltage so that only one of the junctions can exist in the V.noteq.0 state at a time. By use of relatively long junctions, in which current densities are not too high, (column 7, lines 46-58) the minimum switch-back voltage can be "smaller than even half the energy gap voltage". Long junctions, however, imply commensurately small packing densities.
As mentioned previously, a Josephson junction undergoing relaxation oscillations is essentially a self-resetting switch. H. W. Chan et al [IEEE Transactions on Magnetics, Vol. MAG-11, No. 2, p. 770 (1975)] show an elementary logic circuit in which a junction is shunted by a load resistor which is carefully selected to insure resetting. A more complex arrangement, a three-junction interferometer with symmetric split current bias connection, is disclosed by H. H. Zappe [IEEE Transactions on Magnetics, Vol. MAG-13, No. 1, p. 41 (1977)]. In both of these designs the circuit is not oscillating when the input is turned off. Thus, they could be used to perform logic OR or AND functions, but a separate circuit would be required to perform inversion (e.g., NOR, NAND and INVERT). Another aspect of these circuits which severely limits their practical utility is that the input or control signals are used to depress I.sub.J, and the level to which I.sub.J is decreased determines the amplitude of the oscillating output signal. As a consequence, the current level on the output line is not predictable, and in a chain of logic circuits, the design of downstream logic circuits is rendered extremely difficult, if not impossible.